Data processing systems, such as microcontroller or microprocessor integrated circuits, may have an internal instruction pipe which is used to queue incoming instructions that are to be executed. In order to facilitate hardware testing and software program debugging, it is useful for the data processor to provide pipe status information to the data processor's external bus. In this manner, test and debug equipment external to the data processor, such as a development system, is able to monitor status information regarding the instruction pipe.
Prior art data processors have provided pipe status information which indicated whether or not the instruction pipe was empty. This is often sufficient pipe status information for data processors that have short instruction pipes, such as one or two stages. However, this is usually insufficient information for data processors that have a deeper instruction pipe. Some prior art data processors that have deeper instruction pipes have provided pipe status information which indicated when the data processor had a change of instruction flow, that is when the instruction pipe required flushing because a jump or a branch instruction required the old instructions in the instruction pipe to be removed without being executed. As an example, some members of the MC68HC16 and MC68300 families of microcontrollers, available from Motorola, Inc. of Austin, Tex., are able to provide this type of pipe status information on the external bus.
However, for data processors that have instruction pipes deeper than one or two stages, providing pipe status information indicating when the data processor had a change of instruction flow (i.e. indicating when the pipe must be flushed) may not be sufficient for the development system to quickly synchronize with the instruction execution within the data processor. For example, if the software code being executed by the data processor executes a significant amount of straight line code before a branch or jump is encountered, the development system may not be able to quickly synchronize with the data processor and may not be able to quickly determine which instruction the data processor is currently executing.
In some situations, a long delay in synchronizing the development system to the execution of instructions in the data processor may significantly hamper testing and debugging of the data processor. A solution was needed which would allow user visibility to pipe status information as real-time as possible, while allowing the development system to quickly synchronize with instruction execution in the data processor. Quick synchronization would allow the development system to determine which instruction is currently being executed so that instruction tracking may begin as soon as possible. Of course, it is important that the provision of pipe status information not significantly impact the internal operation and speed of the data processor.